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1/21 june 2004 m41t00 serial access timekeeper ? features summary 2.0 to 5.5v clock operating voltage counters for seconds, minutes, hours, day, date, month, years, and century year 2000 compliant software clock calibration automatic switch-over and deselect circuitry i 2 c bus compatible ultra-low battery supply current of 1a low operating current of 300a battery or super-cap back-up battery back-up not recommended for 3.0v applications (capacitor back-up only) operating temperature of ?40 to 85c automatic leap year compensation special software programmable output figure 1. package 8 1 so8 (m) 8-pin soic
m41t00 2/21 table of contents features summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 figure 1. package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 figure 2. logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 figure 3. soic connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 table 1. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 figure 4. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2-wire bus characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 bus not busy.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 start data transfer.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 stop data transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 data valid. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 acknowledge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 5. serial bus data transfer sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 6. acknowledgement sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 7. bus timing requirements sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 2. ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 8. slave address location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 9. read mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 figure 10.alternate read mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 write mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 data retention mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 11.write mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 clock operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 3. register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 clock calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 12.crystal accuracy across temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 13.clock calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 output driver pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 initial power-on defaults. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 maximum rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 4. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 dc and ac parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 5. operating and ac measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 14.ac testing input/output waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 6. capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3/21 m41t00 table 7. dc characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 8. crystal electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 15.power down/up mode ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 9. power down/up ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 10. power down/up trip points dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 package mechanical information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 16.so8 ? 8-lead plastic small package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 11. so8 ? 8-lead plastic small outline package mechanical data. . . . . . . . . . . . . . . . . . . . 18 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 12. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 9 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 13. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
m41t00 4/21 summary description the m41t00 timekeeper ? ram is a low power serial timekeeper with a built-in 32.768khz os- cillator (external crystal controlled). eight bytes of the ram are used for the clock/calendar function and are configured in binary coded decimal (bcd) format. addresses and data are transferred serial- ly via a two-line bi-directional bus. the built-in ad- dress register is incremented automatically after each write or read data byte. the m41t00 clock has a built-in power sense cir- cuit which detects power failures and automatical- ly switches to the battery supply during power failures. the energy needed to sustain the ram and clock operations can be supplied from a small lithium coin cell. typical data retention time is in excess of 5 years with a 50ma/h 3v lithium cell (see data retention mode, page 10 for ac/dc characteristics). the m41t00 is supplied in 8 lead plastic small outline package. figure 2. logic diagram figure 3. soic connections table 1. signal names ai00530 osci v cc m41t00 v ss scl osco sda ft/out v bat 1 sda v ss scl ft/out osco osci v cc v bat ai00531 m41t00 2 3 4 8 7 6 5 osci oscillator input ocso oscillator output ft/out frequency test / output driver (open drain) sda serial data address input / output scl serial clock v bat battery supply voltage v cc supply voltage v ss ground
5/21 m41t00 figure 4. block diagram ai00603 seconds oscillator 32.768 khz voltage sense and switch circuitry serial bus interface divider control logic address register minutes century/hours day date month year control osci osco ft/out v cc v ss v bat scl sda 1 hz
m41t00 6/21 operation the m41t00 clock operates as a slave device on the serial bus. access is obtained by implementing a start condition followed by the correct slave ad- dress (d0h). the 8 bytes contained in the device can then be accessed sequentially in the following order: 1. seconds register 2. minutes register 3. century/hours register 4. day register 5. date register 6. month register 7. years register 8. control register the m41t00 clock continually monitors v cc for an out of tolerance condition. should v cc fall below v so , the device terminates an access in progress and resets the device address counter. inputs to the device will not be recognized at this time to prevent erroneous data from being written to the device from an out of tolerance system. when v cc falls below v so , the device automatically switches over to the battery and powers down into an ultra low current mode of operation to conserve battery life. upon power-up, the device switches from bat- tery to v cc at v so and recognizes inputs. 2-wire bus characteristics this bus is intended for communication between different ics. it consists of two lines: one bi-direc- tional for data signals (sda) and one for clock sig- nals (scl). both the sda and the scl lines must be connected to a positive supply voltage via a pull-up resistor. the following protocol has been defined: ? data transfer may be initiated only when the bus is not busy. ? during data transfer, the data line must remain stable whenever the clock line is high. changes in the data line while the clock line is high will be interpreted as control signals. accordingly, the following bus conditions have been defined: bus not busy. both data and clock lines remain high. start data transfer. a change in the state of the data line, from high to low, while the clock is high, defines the start condition. stop data transfer. a change in the state of the data line, from low to high, while the clock is high, defines the stop condition. data valid. the state of the data line represents valid data when after a start condition, the data line is stable for the duration of the high period of the clock signal. the data on the line may be changed during the low period of the clock signal. there is one clock pulse per bit of data. each data transfer is initiated with a start condition and terminated with a stop condition. the number of data bytes transferred between the start and stop conditions is not limited. the information is transmitted byte-wide and each receiver acknowl- edges with a ninth bit. by definition, a device that gives out a message is called ?transmitter?, the receiving device that gets the message is called ?receiver?. the device that controls the message is called ?master?. the de- vices that are controlled by the master are called ?slaves?. acknowledge. each byte of eight bits is followed by one acknowledge bit. this acknowledge bit is a low level put on the bus by the receiver, whereas the master generates an extra acknowledge relat- ed clock pulse. a slave receiver which is addressed is obliged to generate an acknowledge after the reception of each byte. also, a master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. the device that acknowledges has to pull down the sda line during the acknowledge clock pulse in such a way that the sda line is a stable low dur- ing the high period of the acknowledge related clock pulse. of course, setup and hold times must be taken into account. a master receiver must sig- nal an end-of-data to the slave transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. in this case, the transmitter must leave the data line high to enable the master to generate the stop condition.
7/21 m41t00 figure 5. serial bus data transfer sequence figure 6. acknowledgement sequence ai00587 data clock data line stable data valid start condition change of data allowed stop condition ai00601 data output by receiver data output by transmitter sclk from master start clock pulse for acknowledgement 12 89 msb lsb
m41t00 8/21 figure 7. bus timing requirements sequence note: p = stop and s = start table 2. ac characteristics note: 1. valid for ambient operating temperature: t a = ?40 to 85c; v cc = 2.0 to 5.5v (except where noted). 2. transmitter must internally provide a hold time to bridge the undefined region (300ns max.) of the falling edge of scl. symbol parameter (1) min max unit f scl scl clock frequency 0 100 khz t low clock low period 4.7 s t high clock high period 4 s t r sda and scl rise time 1 s t f sda and scl fall time 300 ns t hd:sta start condition hold time (after this period the first clock pulse is generated) 4s t su:sta start condition setup time (only relevant for a repeated start condition) 4.7 s t su:dat data setup time 250 ns t hd:dat (2) data hold time 0 s t su:sto stop condition setup time 4.7 s t buf time the bus must be free before a new transmission can start 4.7 s ai00589 sda p tsu:sto tsu:sta thd:sta sr scl tsu:dat tf thd:dat tr thigh tlow thd:sta tbuf s p
9/21 m41t00 read mode in this mode, the master reads the m41t00 slave after setting the slave address (see figure 8 ). fol- lowing the write mode control bit (r/w = 0) and the acknowledge bit, the word address an is writ- ten to the on-chip address pointer. next the start condition and slave address are repeated, followed by the read mode control bit (r/w =1). at this point, the master transmitter becomes the master receiver. the data byte which was ad- dressed will be transmitted and the master receiv- er will send an acknowledge bit to the slave transmitter. the address pointer is only increment- ed on reception of an acknowledge bit. the m41t00 slave transmitter will now place the data byte at address a n+1 on the bus. the master re- ceiver reads and acknowledges the new byte and the address pointer is incremented to a n+2 . this cycle of reading consecutive addresses will continue until the master receiver sends a stop condition to the slave transmitter. an alternate read mode may also be implement- ed, whereby the master reads the m41t00 slave without first writing to the (volatile) address point- er. the first address that is read is the last one stored in the pointer (see figure 10., page 10 ). figure 8. slave address location figure 9. read mode sequence ai00602 r/w slave address start a 01000 11 msb lsb ai00899 bus activity: ack s ack ack ack no ack stop start p sda line bus activity: master r/w data n data n+1 data n+x word address (an) slave address s start r/w slave address ack
m41t00 10/21 figure 10. alternate read mode sequence write mode in this mode the master transmitter transmits to the m41t00 slave receiver. bus protocol is shown in figure 11., page 10 . following the start con- dition and slave address, a logic '0' (r/w = 0) is placed on the bus and indicates to the addressed device that word address an will follow and is to be written to the on-chip address pointer. the data word to be written to the memory is strobed in next and the internal address pointer is incremented to the next memory location within the ram on the reception of an acknowledge clock. the m41t00 slave receiver will send an acknowledge clock to the master transmitter after it has received the slave address and again after it has received the word address and each data byte (see figure 8 ). data retention mode with valid v cc applied, the m41t00 can be ac- cessed as described above with read or write cycles. should the supply voltage decay, the m41t00 will automatically deselect, write protect- ing itself when v cc falls (see figure 15., page 17 ). figure 11. write mode sequence ai00895 bus activity: ack s ack ack ack no ack stop start p sda line bus activity: master r/w data n data n+1 data n+x slave address ai00591 bus activity: ack s ack ack ack ack stop start p sda line bus activity: master r/w data n data n+1 data n+x word address (an) slave address
11/21 m41t00 clock operation the eight byte clock register (see table 3 ) is used to both set the clock and to read the date and time from the clock, in a binary coded decimal format. seconds, minutes, and hours are contained within the first three registers. bits d6 and d7 of clock register 2 (hours register) contain the century enable bit (ceb) and the century bit (cb). setting ceb to a '1' will cause cb to toggle, either from '0' to '1' or from '1' to '0' at the turn of the cen- tury (depending upon its initial state). if ceb is set to a '0', cb will not toggle. bits d0 through d2 of register 3 contain the day (day of week). registers 4, 5 and 6 contain the date (day of month), month and years. the final register is the control regis- ter (this is described in the clock calibration sec- tion). bit d7 of register 0 contains the stop bit (st). setting this bit to a '1' will cause the oscillator to stop. if the device is expected to spend a signif- icant amount of time on the shelf, the oscillator may be stopped to reduce current drain. when re- set to a '0' the oscillator restarts within one second. note: in order to guarantee oscillator start-up after the initial power-up, set the st bit to a '1,' then re- set this bit to a '0.' this sequence enables a ?kick start? circuit which aids the oscillator start-up dur- ing worst case conditions of voltage and tempera- ture. the seven clock registers may be read one byte at a time, or in a sequential block. the control register (address location 7) may be accessed in- dependently. provision has been made to assure that a clock update does not occur while any of the seven clock addresses are being read. if a clock address is being read, an update of the clock reg- isters will be delayed by 250ms to allow the read to be completed before the update occurs. this will prevent a transition of data during the read. note: this 250ms delay affects only the clock reg- ister update and does not alter the actual clock time. table 3. register map keys: s = sign bit ft = frequency test bit st = stop bit out = output level x = don?t care ceb = century enable bit cb = century bit note: 1. when ceb is set to '1', cb will toggle from '0' to '1' or from '1' to '0' at the turn of the century (dependent upon the initial value set). when ceb is set to '0', cb will not toggle. address data function/range bcd format d7 d6 d5 d4 d3 d2 d1 d0 0 st 10 seconds seconds seconds 00-59 1 x 10 minutes minutes minutes 00-59 2 ceb (1) cb 10 hours hours century/hours 0-1/00-23 3 xxxxx day day 01-07 4 x x 10 date date date 01-31 5 x x x 10 m. month month 01-12 6 10 years years year 00-99 7 out ft s calibration control
m41t00 12/21 clock calibration the m41t00 is driven by a quartz controlled oscil- lator with a nominal frequency of 32,768hz. the devices are tested not to exceed 35 ppm (parts per million) oscillator frequency error at 25c, which equates to about 1.53 minutes per month. with the calibration bits properly set, the accuracy of each m41t00 improves to better than 2 ppm at 25c. the oscillation rate of any crystal changes with temperature (see figure 12., page 13 ). most clock chips compensate for crystal frequency and tem- perature shift error with cumbersome trim capaci- tors. the m41t00 design, however, employs periodic counter correction. the calibration circuit adds or subtracts counts from the oscillator divider circuit at the divide by 256 stage, as shown in fig- ure 13., page 13 . the number of times pulses are blanked (subtracted, negative calibration) or split (added, positive calibration) depends upon the value loaded into the five-bit calibration byte found in the control register. adding counts speeds the clock up, subtracting counts slows the clock down. the calibration byte occupies the five lower order bits (d4-d0) in the control register (addr 7). this byte can be set to represent any value between 0 and 31 in binary form. bit d5 is a sign bit; '1' indi- cates positive calibration, '0' indicates negative calibration. calibration occurs within a 64minute cycle. the first 62 minutes in the cycle may, once per minute, have one second either shortened by 128 or lengthened by 256 oscillator cycles. if a bi- nary '1' is loaded into the register, only the first 2 minutes in the 64 minute cycle will be modified; if a binary 6 is loaded, the first 12 will be affected, and so on. therefore, each calibration step has the effect of adding 512 or subtracting 256 oscillator cycles for every 125,829,120 actual oscillator cycles, that is +4.068 or ?2.034 ppm of adjustment per calibra- tion step in the calibration register. assuming that the oscillator is in fact running at exactly 32,768hz, each of the 31 increments in the calibration byte would represent +10.7 or ?5.35 seconds per month which corresponds to a total range of +5.5 or ?2.75 minutes per month. two methods are available for ascertaining how much calibration a given m41t00 may require. the first involves simply setting the clock, letting it run for a month and comparing it to a known accu- rate reference (like wwv broadcasts). while that may seem crude, it allows the designer to give the end user the ability to calibrate his clock as his en- vironment may require, even after the final product is packaged in a non-user serviceable enclosure. all the designer has to do is provide a simple utility that accessed the calibration byte. the second approach is better suited to a manu- facturing environment, and involves the use of some test equipment. when the frequency test (ft) bit, the seventh-most significant bit in the control register, is set to a '1', and the oscillator is running at 32,768hz, the ft/out pin of the device will toggle at 512hz. any deviation from 512hz in- dicates the degree and direction of oscillator fre- quency shift at the test temperature. for example, a reading of 512.01024hz would in- dicate a +20 ppm oscillator frequency error, requir- ing a ?10(xx001010) to be loaded into the calibration byte for correction. note that setting or changing the calibration byte does not affect the frequency test output frequency.
13/21 m41t00 figure 12. crystal accuracy across temperature figure 13. clock calibration ai00999b ?160 0 10203040506070 frequency (ppm) temperature c 80 ?10 ?20 ?30 ?40 ?100 ?120 ?140 ?40 ?60 ?80 20 0 ?20 ? f = k x (t ?t o ) 2 k = ?0.036 ppm/ c 2 0.006 ppm/ c 2 t o = 25 c 5 c f ai00594b normal positive calibration negative calibration
m41t00 14/21 output driver pin when the ft bit is not set, the ft/out pin be- comes an output driver that reflects the contents of d7 of the control register. in other words, when d6 of location 7 is a zero and d7 of location 7 is a zero and then the ft/out pin will be driven low. note: the ft/out pin is open drain which re- quires an external pull-up resistor. initial power-on defaults upon initial application of power to the device, the ft bit will be set to a '0' and the out bit will be set to a '1'. all other register bits will initially power-on in a random state. maximum rating stressing the device above the rating listed in the ?absolute maximum ratings? table may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicat- ed in the operating sections of this specification is not implied. exposure to absolute maximum rat- ing conditions for extended periods may affect de- vice reliability. refer also to the stmicroelectronics sure program and other rel- evant quality documents. table 4. absolute maximum ratings note: 1. for so package, standard (snpb) lead finish: reflow at peak temperature of 225c (total thermal budget not to exceed 180 c for between 90 to 150 seconds). 2. for so package, lead-free (pb-free) lead finish: reflow at peak temperature of 260c (total thermal budget not to exceed 245 c for greater than 30 seconds). caution: negative undershoots below ?0.3v are not allow ed on any pin while in the battery back-up mode. symbol parameter value unit t a ambient operating temperature ?40 to 85 c t stg (1) storage temperature (v cc off, oscillator off) ?55 to 125 c v io input or output voltages ?0.3 to 7 v v cc supply voltage ?0.3 to 7 v i o output current 20 ma p d power dissipation 0.25 w
15/21 m41t00 dc and ac parameters this section summarizes the operating and mea- surement conditions, as well as the dc and ac characteristics of the device. the parameters in the following dc and ac characteristic tables are derived from tests performed under the measure- ment conditions listed in the relevant tables. de- signers should check that the operating conditions in their projects match the measurement condi- tions when using the quoted parameters. table 5. operating and ac measurement conditions note: output hi-z is defined as the point where data is no longer driven. figure 14. ac testing input/output waveform table 6. capacitance note: 1. effective capacitance measured with power supply at 5v; sampled only, not 100% tested. 2. at 25c, f = 1mhz. 3. outputs deselected. parameter m41t00 unit supply voltage (v cc ) 2.0 to 5.5 v ambient operating temperature (t a ) ?40 to 85 c load capacitance (c l ) 100 pf input rise and fall times 5ns input pulse voltages 0.2v cc to 0.8v cc v input and output timing ref. voltages 0.3v cc to 0.7v cc v ai02568 0.8v cc 0.2v cc 0.7v cc 0.3v cc symbol parameter (1,2) min max unit c in input capacitance (scl) 7 pf c out (3) output capacitance (sda, ft/out) 10 pf t lp low-pass filter input time constant (sda and scl) 250 1000 ns
m41t00 16/21 table 7. dc characteristics note: 1. valid for ambient operating temperature: t a = ?40 to 85c; v cc = 2.0 to 5.5v (except where noted). 2. stmicroelectronics recommends the rayovac br1225 or br1632 (or equi valent) as the battery supply. 3. after switchover (v so ), v bat (min) can be 2.0v for crystal with r s = 40k ? . 4. for rechargeable back-up, v bat (max) may be considered v cc . table 8. crystal electrical characteristics note: 1. these values are externally supplied. stmicroelectronics recommends the kds dt-38: 1ta/1tc252e127, tuning fork type (thr u- hole) or the dmx-26s: 1tjs125fh2a212, (smd) quartz crystal for in dustrial temperature operations. kds can be contacted at kou- hou@kdsj.co.jp or http://www.kdsj.co.jp for further information on this crystal type. 2. load capacitors are integrated within the m41t00. circuit board layout considerations for the 32.768khz crystal of minimum tr ace lengths and isolation from rf generatin g signals should be taken into account. symbol parameter test condition (1) min typ max unit i li input leakage current 0v v in v cc 1 a i lo output leakage current 0v v out v cc 1 a i cc1 supply current switch frequency = 100khz 300 a i cc2 supply current (standby) scl, sda = v cc ? 0.3v 70 a v il input low voltage ?0.3 0.3 v cc v v ih input high voltage 0.7 v cc v cc + 0.5 v v ol output low voltage i ol = 3ma 0.4 v pull-up supply voltage (open drain) ft/out 5.5 v v bat (2) battery supply voltage 2.5 (3) 3 3.5 (4) v i bat battery supply current t a = 25c, v cc = 0v, oscillator on, v bat = 3v 0.8 1 a symbol parameter (1,2) min typ max unit f o resonant frequency 32.768 khz r s series resistance 60 k ? c l load capacitance 12.5 pf
17/21 m41t00 figure 15. power down/up mode ac waveforms table 9. power down/up ac characteristics note: 1. valid for ambient operating temperature: t a = ?40 to 85c; v cc = 2.0 to 5.5v (except where noted). 2. v cc fall time should not exceed 5mv/s. table 10. power down/up trip points dc characteristics note: 1. valid for ambient operating temperature: t a = ?40 to 85c; v cc = 2.0 to 5.5v (except where noted). 2. all voltages referenced to v ss . 3. in 3.3v application, if initial battery voltage is 3.4v, it may be necessary to reduce battery voltage (i.e., through wave soldering the battery) in order to avoid inadvertent switchover/deselection for v cc ? 10% operation. 4. switch-over and deselect point. symbol parameter (1) min max unit t pd scl and sda at v ih before power down 0ns t rec (2) scl and sda at v ih after power up 10 s symbol parameter (1,2) min typ max (3) unit v so (4) battery back-up switchover voltage v bat ? 0.80 v bat ? 0.50 v bat ? 0.30 v ai00596 v cc trec tpd v so sda scl don't care
m41t00 18/21 package mechanical information figure 16. so8 ? 8-lead plastic small package outline note: drawing is not to scale. table 11. so8 ? 8-lead plastic small outline package mechanical data symb mm inches typ min max typ min max a 1.35 1.75 0.053 0.069 a1 0.10 0.25 0.004 0.010 b 0.33 0.51 0.013 0.020 c 0.19 0.25 0.007 0.010 d 4.80 5.00 0.189 0.197 e 3.80 4.00 0.150 0.157 e 1.27 ? ? 0.050 ? ? h 5.80 6.20 0.228 0.244 h 0.25 0.50 0.010 0.020 l 0.40 0.90 0.016 0.035 0 8 0 8 n8 8 cp 0.10 0.004 so-a e 8 ddd b e a d c l a1 1 h h x 45? a2
19/21 m41t00 part numbering table 12. ordering information scheme for other options, or for more information on any aspect of this device, please contact the st sales office nearest you. example: m41t 00 m 6 e device type m41t supply voltage and write protect voltage 00 = v cc = 2.0 to 5.5v package m = so8 (150 mils width) temperature range 6 = ?40 to 85c shipping method blank = tubes (not for new design - use e) e = lead-free package (eco pack ? ), tubes f = lead-free package (eco pack ? ), tape & reel tr = tape & reel (not for new design - use f)
m41t00 20/21 revision history table 13. document revision history m41t00, 41t00, t00, nvram, nvram, nvram, nvram, nvram, nvram, nvram, nvram, nvram, nvram, nvram, nvram, nvram, nvram, nvram, nvram, nvram, nvram, nvram, nvram, nvram, nvram, nvram, nvram, nvram, nvram, nvram, nvram, nvram, nvram, nvram, nvram, nvram, nvram, nvram, nvram, nvram, nvram, nvram, nvram, nvram, nvram, nvram, nvram, nvram, nvram, nvram, nvram, nvram, nvram, timekeeper, timekeeper, timekeeper, timekeeper, timekeeper, timekeeper, timekeeper, timekeeper, timekeeper, timekeeper, timekeeper, timekeeper, timekeep- er, timekeeper, timekeeper, timekeeper, timekeeper, timekeeper, timekeeper, timekeeper, timekeeper, time- keeper, timekeeper, timekeeper, timekeeper, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, ser ial, serial, serial, serial, serial, serial, seri al, serial, serial, serial, serial, serial, serial, seri al, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, seri al, serial, serial, serial, serial, serial, serial, seri al, serial, serial, serial, serial, serial, serial, access, access, access, access, access, access, access, access, access, access, access, access, access, access, access, access, access, ac- cess, access, access, access, access, access, access, access, access, access, access, access, access, access, access, access, a c- cess, access, access, access, access, access, access, access, access, access, access, access, access, access, access, access, access, access, access, access, access, access, access, access, access, access, access, access, access, access, access, access, ac- cess, access, access, access, access, access, access, access, access, access, i2c, i2c, i2c, i2c, i2c, i2c, i2c, i2c, i2c, i2c, i2c, i2c, i2c, i2c, i2c, i2c, i2c, i2c, i2c, i2c, i2c, i2c, i2c, i2c, i2c, i2c, i2c, i2c, i2c, i2c, i2c, i2c, i2c, i2c, i2c, i2c, i2c, i2 c, i2c, i2c, i2c, i2c, i2c, i2c, i2c, leap year, leap year, leap year, leap year, leap year, software, software, software, software, software, so ftware, soft- ware, software, software, software, software, software, software, software, software, software, software, software, software, s oftware, soft- ware, software, software, software, software, software, software, software, software, software, software, software, software, s oftware, software, software, software, software, software, software, software, software, software, software, software, software, softwar e, software, software, software, software, software, software, software, software, software, software, software, software, software, softwar e, software, software, software, software, software, software, software, software, software, software, software, software, software, softwar e, software, software, software, software, software, software, software, software, software, software, software, software, software, softwar e, software, software, software, software, software, software, software, software, software, software, software, software, software, softwar e, software, software, software, software, software, software, software, software, software, software, software, software, software, softwar e, software, software, software, software, software, software, software, software, software, software, software, software, software, softwar e, software, software, software, software, clock, clock, clock, clock, clock, clock, clock, clock, clock, clo ck, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, cl ock, clock, clock, clock, clock, clock, cl ock, clock, clock, clock, clock, clock, c lock, clock, clock, clock, clock, clock, clock, clock, clock, clock, cl ock, clock, clock, clock, clock, clock, cl ock, clock, clock, clock, clock, clock, c lock, clock, clock, clock, clock, clock, clock, clock, clock, clock, cl ock, clock, clock, clock, clock, clock, cl ock, clock, clock, clock, clock, clock, c lock, clock, clock, clock, clock, clock, clock, clock, clock, clock, cl ock, clock, clock, clock, clock, clock, cl ock, clock, clock, clock, clock, clock, c lock, clock, clock, clock, clock, clock, clock, clock, clock, industrial, industrial, in dustrial, industrial, industrial, industrial, industrial, industri al, industrial, industrial, in- dustrial, industrial, industrial, industrial, industrial, temperat ure, temperature, temperature, temperature, temperature, temp erature, temperature, temperature, temperature, temperature, temperature, temperature, temperature, temperature, temperature, tempera- ture, temperature, temperature, temperature, temperature, temper ature, temperature, temperature, temperature, temperature, tem- perature, temperature, temperature, temperature, temperature, te mperature, temperature, temperature, temperature, temperature, temperature, temperature, temperature, temperature, temperatur e, microprocessor, microprocessor, microprocessor, microprocessor , microprocessor, microprocessor, microprocessor, microprocessor, microprocessor, microprocessor, microprocessor, microprocessor, micro- processor, microprocessor, microprocessor, microprocessor, microprocessor, microprocessor, microprocessor, microprocessor, 2v, 2v, 2v, 2v, 2v, 2v, 2v, 2v, 2v, 2v, 2v, 2v, 2v, 2v, 2v, 2v, 2v, 2v, 2v, 2v, 2v, 2v, 2v, 2v, 2v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, dip, dip, dip, dip, dip, dip, dip, dip, dip, dip, dip, dip, dip, dip, dip, dip, dip, dip, dip, dip, dip, dip, dip, dip, dip, dip, dip, dip, dip, dip date version revision details march 1999 1.0 first issue 05/15/00 1.1 ac characteristic conditions changed (table 2 ) 07/25/00 1.2 crystal electrical characteristics: r s max changed (table 8 ) 12/12/00 1.3 edit v so (table 10 ) 01/24/01 2.0 reformatted 02/27/01 3.0 document status changed 07/17/01 3.1 change to dc and ac characteristics (tables 7 , 2 ); added temp./voltage info. to tables (table 6 , 7 , 8 , 2 , 9 , 10 ) 11/27/01 3.2 features, (page 1); dc characteristics (table 7 ); crystal electrical (table 8 ); power down/up trip points (table 10 ) changes; add table footnote (table 10 ) 01/21.02 3.3 fix table footnotes (table 7 , 8 ) 05/13/02 3.4 modify reflow time and temperature footnote (table 4 ) 06/05/02 3.5 corrected operating voltage (table 12 ) 07/03/02 3.6 modify ?clock operation? text, crystal electrical characteristics table footnote (table 8 ) 11/07/02 3.7 correct figure name (figure 1 ) 15-jun-04 4.0 reformatted; add lead-free information; update characteristics (figure 12 ; table 4 , 7 , 12 )
21/21 m41t00 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replac es all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2004 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states www.st.com

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